Many applications such as portable telecommunication, imaging, and video systems use Analog-to-Digital Converters (ADC's). These applications often require an ADC with 10 bits or more of resolution. In addition to a high resolution, low power and high speed are also desirable.
FIGS. 1A-1D show various kinds of Analog-to-Digital Converters (ADC's) that have been used in a variety of applications. In FIG. 1A, a Flash ADC uses many comparators 14 in parallel to compare an analog input voltage VIN to various voltages generated by applying a reference voltage VREF to a voltage divider or resistors 16 in series. Decoder 122 converts the thermometer code from comparators 14 to an N-bit binary value. The flash ADC is fast, but requires a large area due to the parallel comparators 14, which also draw a large amount of power. Also, the flash ADC may require a separate sample-and-hold circuit (not shown) since it may not store signals.
In FIG. 1B, a pipeline ADC has several stages 110, 110′, 110″. Each stage generates a few bits such as 2 binary bits. FIG. 1C shows that a stage 110 has a sample and hold 12, an ADC 20 that converts the analog voltage to a 2-bit digital value, which is then converted back to analog by Digital-to-Analog Converter (DAC) 30 and subtracted from the sampled analog voltage by analog subtractor 26. The remaining voltage difference or residual voltage is amplified by amplifier 28 and applied as the analog voltage input to the next stage.
ADC 20 can be a small flash ADC such as a sigma-delta modulator, a small Successive-Approximation Register (SAR), or a 2-bit flash ADC. Since ADC 20 has only 2 bits and 2 comparators, power, cost, and area are reduced compared with the many parallel comparisons of the larger flash ADC of FIG. 1A. However, amplifier 28 must be very accurate and have a high performance, causing the power dissipation to increase.
FIG. 1D shows a SAR ADC. SAR state machine and control logic 124 includes an N-bit register that is adjusted every clock cycle until the correct result is obtained. The current digital value in the SAR is applied to DAC 34 and converted to an analog voltage that is compared to the input analog voltage by comparator 14. The result of comparator 14 is used to adjust the digital SAR value in SAR state machine and control logic 124. In each successive cycle, a next lower-significant binary bit can be tested. In general, the number of clock cycles required is equal to the number of binary bits. A SAR ADC is very efficient in power, area, and cost, but is complex to operate and has speed and resolution limitations due to the serial nature of its processing and accumulated comparator noise.
Each of the ADC architectures has drawbacks. The flash ADC is fast but has a lower resolution and requires high power and area. The pipeline ADC is not as fast as the flash ADC, but has a high resolution while being complex and relatively inefficient. The SAR ADC is very efficient in area and power, but is slow and limited to a moderate resolution.
What is desired is a hybrid ADC architecture that is fast and has a high resolution while still being efficient. A hybrid ADC with multiple stages is desired that uses a smaller flash ADC for speed, but also uses a SAR for efficiency. A pipelined hybrid SAR and flash ADC is desirable.